7.4 A 0.027mm² 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fs_rms Jitter and -74.2dBc Reference Spur

A 6-GHz 78-fs$_{\mathrm{RMS}}$ Double-Sampling PLL With Low-Ripple Bootstrapped DSPD and Retimer-Less MMD Achieving $-$92-dBc Reference Spur and $-$258-dB FOM

A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering

A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit

A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving −80-dBc Reference Spur and −259-dB FoM with 12-pF Input Load

Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit

Investigation and Improvement on Self-dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis

Power-Efficient RF and mm-Wave VCOs/PLL

A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving −63-dBc Reference Spur, 175-fs RMS Jitter and −240-dB FOMjitter

A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push–Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM

A 0.003-mm² 440fs_RMS-Jitter and −64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector

A Calibration-Free, Reference-Buffer-Free, Type-I Narrow-Pulse-Sampling PLL With −78.7-dBc REF Spur, −128.1-dBc/Hz Absolute In-Band PN and −254-dB FOM

16.8 A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur

A 0.003-mm² 440fs_RMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS

A 0.0071-mm² 10.8ps_pp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis