A full-transistor fine-grain multilevel delay element with compact regularity layout

A Watt-level Broadband Power Amplifier in GaAs HBT Process

Density Optimization for Analog Layout Based on Transistor-Array

Routable and Matched Layout Styles for Analog Module Generation

Two 1 novel automatic generation methods for analog layout—a symmetrical twin-row method for MOS transistors and a twisted common-centroid method for capacitor arrays—are introduced. Based on the proposed layout styles and the corresponding algorithms, the symmetry and common-centroid placement patterns for analog devices are realized to guarantee matching properties. On this basis, as the most prominent contribution of this article, channel routing-based algorithms for the proposed layout styles are presented and could achieve 100% routability due to well-arranged devices and corresponding low routing complexity. The algorithms benefits include a small layout area that maximizes the diffusion-sharing of MOS transistors and less routing layer usage for common-centroid device arrays. Moreover, we successfully applied our algorithms to the layout designs of two typical analog modules including a two-stage operating amplifier and a Successive Approximation Register Analog-to-Digital Converter (SAR-ADC). The generated layouts and the circuit simulation results demonstrate the effectiveness of our algorithms in terms of their routability and matching properties. Our algorithms can also be extended to apply to a variety of essential MOS analog circuits.

Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit

Explicit layout pattern density controlling based on transistor-array-style

Analysis and reduction of SRAM PUF Bit Error Rate

Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration

Soft-coupling with A/D and D/A converters for analog reconfigurable system

Routability of twisted common-centroid capacitor array under signal coupling constraints

Layout-dependent effect evaluation of transistor array-style phase locked loop

A multi-functional memory unit with PLA-based reconfigurable decoder

Twin-row-style for MOS analog layout

A Ku-band wide-tuning-range high-output-power VCO in InGaP/GaAs HBT technology

A rigorous peeling algorithm for direct parameter extraction procedure of HBT small-signal equivalent circuit

CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects

Layout-Aware Variability Characterization of CMOS Current Sources

Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis

D-A converter based variation analysis for analog layout design

Variation-Tolerant Decomposition of MOS Transistor