Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory

DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach

Energy-aware loops mapping on multi-vdd CGRAs without performance degradation

A Fast and Power-Efficient Memory-Centric Architecture for Affine Computation

Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures

Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures

Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures

Joint Affine Transformation and Loop Pipelining for Mapping Nested Loop on CGRAs

RNA: A Reconfigurable Architecture for Hardware Neural Acceleration

Exploiting Outer Loop Parallelism of Nested Loop on Coarse-Grained Reconfigurable Architectures

Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms

Map-reduce inspired loop parallelization on CGRA

Affine transformations for communication and reconfiguration optimization of loops on CGRAs

An inductive-coupling interconnected application-specific 3D NoC design

Design and Implementation of an SD Interface to Multiple-Target Interface Bridge

Polyhedral model based mapping optimization of loop nests for CGRAs

Key techniques of recon gurable computing processor

Performance evaluation modeling for reconfigurable processor

Battery aware tasks allocating algorithm for multi-battery operated system

A data-flow graph generation algorithm for a coarse-grained reconfigurable processor

Compiler framework for reconfigurable computing system

Optimizing buffer usage for Networks-on-Chip design

Template-based compilation for coarse-grained reconfigurable processor